The present invention relates to a semiconductor device and method of manufacturing the same, particularly, to a semiconductor device provided with an element isolation structure having shallow trench isolations with different widths and a method of manufacturing the same.
In order to electrically insulate respective elements formed over a semiconductor substrate, a shallow trench isolation (STI) for element isolation is formed in the semiconductor substrate, and an insulating film such as an oxide film is embedded into the gap for the shallow trench isolation. In the process of embedding the insulating film into the gap for the shallow trench isolation, a technique of embedding the insulating film into a gap for a shallow trench isolation having a high aspect ratio without generating a void is demanded, along with the miniaturization and density growth of patterns.
Until now, as a method of embedding an insulating film into the gap for the shallow trench isolation, a high density plasma chemical vapor deposition method (hereinafter, denoted as an “HDP-CVD method”) has been employed. However, it has become difficult to embed an insulating film into a gap for a shallow trench isolation having a high aspect ratio without generating a void or seam.
Consequently, a technique is employed, in which a shallow trench isolation having a high aspect ratio is embedded by a sub-atmospheric chemical vapor deposition method (hereinafter, denoted as an “SA-CVD method”) using O3-TEOS (Tetra Ethyl Ortho Silicate), or a spin on dielectric method (hereinafter, denoted as an “SOD method”) using polysilazane.
Moreover, as a method of embedding a silicon oxide film into a gap for a shallow trench isolation having a high aspect ratio without causing deterioration of electrical characteristics (such as deterioration of an isolation withstand voltage) and without generating a void, a technique combining the SOD method and the HDP-CVD method is proposed.
For example, Japanese Patent Laid-Open No. 2003-031650 (Patent Document 1) proposes a technique of embedding the shallow trench isolation by embedding a polysilazane film by the SOD method into the gap for the shallow trench isolation, then subjecting the polysilazane film to etch back, and forming an oxide film over the polysilazane by the HDP-CVD method. Japanese Patent Laid-Open No. 2000-183150 (Patent Document 2) proposes a technique in which the etch back of the polysilazane film embedded into the gap for the shallow trench isolation by the SOD method is performed by O2 plasma.
Japanese Patent Laid-Open No. 2000-114362 (Patent Document 3) proposes a technique in which a CVD film with a low etching rate is formed over a polysilazane film embedded into the gap for the shallow trench isolation in order to eliminate a hollow of the shallow trench isolation caused by a high wet etching rate of the polysilazane film embedded into the gap for the shallow trench isolation by the SOD method. Japanese Patent Laid-Open No. 2007-142311 (Patent Document 4) proposes a technique in which the shallow trench isolation is embedded by embedding a silicon-rich oxide film into the bottom portion of the gap for the shallow trench isolation by the SOD method using polysilazane and, over it, forming an oxide film by the HDP-CVD method.